1. Field of the Invention
The present invention generally relates to communication control devices, and more particularly to a communication control device which receives an asynchronous packet from an IEEE 1394 serial bus, and stores the received asynchronous packet in a receive FIFO unit, in which an acknowledge signal asserting whether reception of an asynchronous packet is allowed or denied in response to the asynchronous packets stored in the receive FIFO unit is sent back to the IEEE 1394 serial bus, and to a communication control method.
2. Description of the Related Art
A typical communication control device is illustrated in FIG. 2. An IEEE 1394 link core 1 includes an asynchronous packet receiving circuit 2 for receiving asynchronous packets from an IEEE 1394 serial bus, and an acknowledge generating circuit 3.
The asynchronous packets received by the asynchronous packet receiving circuit 2 are passed to a receive FIFO (First-In First-Out) unit 4 through an ON/OFF switch 6, and are then stored therein. The ON/OFF switch 6 serves as a controller for controlling whether or not the asynchronous packets received by the asynchronous packet receiving circuit 2 are stored in the receive FIFO unit 4. The asynchronous packets read from the receive FIFO unit 4 are transferred to a microcomputer 7 for signal processing using software running on the microcomputer 7.
The switch 6 is turned on/off in response to a control signal from a determination circuit 5, as described below. A gate circuit may be provided in place of the switch 6. Alternatively, in response to a control signal from the determination circuit 5, the receive FIFO unit 4 may be directly controlled as to whether or not the asynchronous packets received by the asynchronous packet receiving circuit 2 are stored in the receive FIFO unit 4. In the latter case, the receive FIFO unit 4 also serves as a controller.
The determination circuit 5 determines whether reception of asynchronous packets that are to be received by the asynchronous packet receiving circuit 2 is allowed or not. Here, the size of an asynchronous packet which is to be received by the asynchronous packet receiving circuit 2 is designated as Pin, the size of asynchronous packets currently stored in the receive FIFO unit 4 is designated as Pnow, and the maximum size of packets which can be stored in the receive FIFO unit 4 is designated as Pmax.
Based on the Pin data from the asynchronous packet receiving circuit 2, and the Pnow data and Pmax data from the receive FIFO unit 4, the determination circuit 5 determines that reception of the new asynchronous packet by the asynchronous packet receiving circuit 2 is denied when Pmax<Pnow+Pin. In this case, the determination circuit 5 also allows the switch 6 to be turned off. When Pmax≧Pnow+Pin, however, the determination circuit 5 determines that reception of the new asynchronous packet by the asynchronous packet receiving circuit 2 is allowed. In this case, the determination circuit 5 also allows the switch 6 to be turned on. These determination results are forwarded to the acknowledge generating circuit 3.
Upon a receipt of a flag indicating the determination result of the determination circuit 5, the acknowledge generating circuit 3 generates acknowledge (b) indicating whether reception of the new asynchronous packet (a) is allowed or denied, and sends the acknowledge (b) back to the IEEE 1394 serial bus. Acknowledge (b) includes “acknowledge complete (or acknowledge pending)” when the flag indicates a high logic (H) output, and “acknowledge busy” when the flag indicates a low logic (L) output.
Since the foregoing communication control device provides a fixed maximum size of packets which can be stored in the receive FIFO unit 4, some problems occur when the asynchronous packet read from the receive FIFO unit 4 is passed to the microcomputer 7 for signal processing using software running on the microcomputer 7.
If the microcomputer 7 has a low throughput relative to the maximum size of packets which can be stored in the receive FIFO unit 4, or when the microcomputer 7 maintains a lower throughput only for a certain period, the receive FIFO unit 4 has the capacity enough to store the received asynchronous packet. Accordingly, the acknowledge generating circuit 3 would generate “acknowledge complete” or “acknowledge pending” representing that reception of a new asynchronous packet is allowed, but not generate “acknowledge busy” representing that reception of a new asynchronous packet is denied.
Since the throughput of the microcomputer 7 for the asynchronous packet is low, a period of more than 100 ms is required for a sequence of procedures in which the microcomputer 7 starts processing the asynchronous packet, terminates once, again starts processing the asynchronous packet when storage is allowed in the receive FIFO unit 4, and terminates. Because the period of more than 100 ms is outside that specified by a split-transaction protocol, a protocol error occurs, possibly leading to a connection problem.
On the other hand, if the microcomputer 7 has a high throughput relative to the maximum size of packets which can be stored in the receive FIFO unit 4, or when the microcomputer 7 maintains a higher throughput only for a certain period, asynchronous packets in excess of the maximum packet-storage size would not be stored, and such a high throughput of the microcomputer 7 for the asynchronous packets is not fully utilized.
As used herein, the period during which the microcomputer 7 maintains a higher (lower) throughput means the period during which the processing of the microcomputer 7 is influenced (is not influenced) by any other software.
Accordingly, a communication control device may receive an asynchronous packet from an IEEE 1394 serial bus, store the received asynchronous packet in a FIFO unit 4, and thereafter generate an acknowledge signal asserting whether reception of an asynchronous packet is allowed or denied. An apparatus incorporating such a communication control device is associated with a problem when a microcomputer contained therein does not provide balance between the throughput and the maximum size of asynchronous packets which can be stored in the FIFO unit 4 of the communication control device, the problem being that a protocol error possibly occurs or the throughput of the microcomputer for asynchronous packets may not be sufficiently utilized.